Decodificator - cod sursa

Decodificator

Codul 1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity dec_74xl38 is

port (Gl : in STD_LOGIC;

G2A : in STD_LOGIC;

G2B : in STD_LOGIC; --intr?ri de validare

A: in STD_LOGIC_vector (2 downto 0); -- intr?ri de selec?ie

Y_L: out STD_LOGIC_vector (0 to 7)); -- ie?iri decodate

end entity dec_74xl38;

architecture var_1 of dec_74xl38 is

signal Y_L_i: STD_LOGIC_vector (0 to 7); -- semnal copie a ie?irii

begin

with A select Y_L_i <=

'01111111' when '111', -- opt cazuri posibile

'10111111' when '011',

'11011111' when '101',

'11101111' when '001',

'11110111' when '110',

'11111011' when '010',

'11111101' when '100',

'11111110' when '000',

'11111111' when others;

Y_L <= Y_L_i    when (Gl and (not G2A) and (not G2B) ) = '1' else '11111111' ;

end architecture var_1;

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