Memorie SRAM 16x8 - Codul in Xilinx

Memorie SRAM 16x8

Codul

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ram16_8 is

port (Address: in std_logic_vector (3 downto 0);

-- Address: in INTEGER;

Data: inout std_logic_vector(7 downto 0);

CLK, CS, WE, OE: in std_ulogic);

end ram16_8;

architecture Behavioral of ram16_8 is

signal data_In : std_logic_vector(7 downto 0);

signal data_out : std_logic_vector(7 downto 0);

begin

p0: process (CLk) is

type ram_array is array (0 to 15) of

std_logic_vector(7 downto 0);

variable mem: ram_array;

variable address_v : integer;

begin

if clk'event and clk ='1' then

address_v := Conv_integer (address);

if cs = '0' then

if oe='0'and we = '1' then

Data_out <= mem(address_v);

elsif oe='1'and we = '0' then

mem(address_v) := Data_in;

else null;

end if;

end if;

end if;

end process p0;

p1:process (CS,OE, WE, Data, data_in, data_out)

begin

if cs = '0' then

if oe='0'and we = '1' then

data <= data_out;

elsif oe='1'and we = '0' then

data <= (others => 'Z');

data_in <= data;

else

data <= (others => 'Z');

end if;

end if;

end process p1;

end Behavioral;

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